1. Field of the Invention
The present invention relates to a semiconductor memory device with a large memory capacity, and, more particularly, to a semiconductor memory device having an improved noise suppressing design.
2. Description of the Related Art
As the memory capacity of conventional semiconductor memory devices increase, the number of internal circuits operating simultaneously in write mode, read mode and cell-data self-refresh mode likewise increase. Unfortunately, accompanying the increased memory capacity of such devices is an increase in the level of noise or interference created by the power supplied to the semiconductor's internal circuits. Consequently, with large capacity semiconductor memory devices, it is necessary to incorporate circuits in the semiconductor that suppress power supply related noise.
FIG. 1 shows the general structure of an ordinary DRAM. Control signals /RAS (Row Address Strobe) and /CAS (Column Address Strobe), input from an external device (not shown) and supplied to an address buffer 1, control the operation of the DRAM. In particular, the control signal /RAS is input to the address buffer 1 as a signal to latch the row address, while the control signal /CAS is input to the address buffer 1 as a signal to latch the column address. Both of the control signals /RAS and /CAS are input to an I/O buffer 2: /RAS as an enable signal and /CAS as an I/O control signal. Both signals /RAS and /CAS are also input to a write clock generator 3: /RAS as an enable signal and /CAS as a signal to latch a write enable signal /WE.
Based on the control signals /RAS and /CAS, address signals A0 to A9 input to the address buffer 1 are latched in the address buffer 1 and are output therefrom to a row decoder 4 and a column decoder 5. Based on the address signals A0 to A9, the row decoder 4 and column decoder 5 select specific memory cells from among a plurality of memory cells in a memory cell array 6. In cell-data read mode, cell data read from the selected memory cells are output as output data, Dout, via a sense amplifier, I/O gate 7 and the I/O buffer circuit 2. In data write mode, write data, Din, input to the I/O buffer circuit 2, is written in the selected memory cells in the memory cell array 6 via the sense amplifier and I/O gate 7. The I/O buffer circuit 2 is controlled based on a write enable signal /WE, which is input via the write clock generator 3 to the I/O buffer circuit 2, and the aforementioned control signals /RAS and /CAS.
The DRAM further includes a self-refresh controller 8, which generates row and column address signals during self-refresh mode operations and outputs the address signals to the respective row decoder 4 or column decoder 5. This mode of operation is different from either write or read operations.
FIG. 2 shows the specific constitution of memory cells in the memory cell array 6 and the sense amplifier and I/O gate 7. Each of the memory cells C is connected to a word line WL and one pair of bit lines BL and /BL. When the row decoder 4 selects a word line WL and the column decoder 5 selects a specific pair of bit lines BL and /BL, it results in the selection of a particular memory cell C in the memory cell array 6. The bit lines BL and /BL are connected to a sense amplifier 9. This sense amplifier 9 comprises P channel MOS transistors Tr1 and Tr2 and N channel MOS transistors Tr3 and Tr4, and is enabled based on a high potential supply power PSG and a low potential supply power NSG.
The sense amplifier 9 is supplied with both a high potential supply voltage PSG from a power supply Vcc via the PMOS transistor Tr5 and with a low potential supply voltage NSG from the ground Vss via the NMOS transistor Tr6. An enable signal generator 20 provided in the DRAM generates a sense amplifier enable signal LE based on the control signals /CAS and/or /RAS supplied thereto. The sense amplifier enable signal LE is input to the gate of the transistor Tr6 directly and to the gate of the transistor Tr5 via an inverter 10a. That is, the transistors Tr5 and Tr6 respectively receive complementary enable signals /LE and LE.
The reading operation of this DRAM will be described with reference to FIG. 3. With the bit lines BL and /BL reset to the half Vcc, the word line WL is selected and pulled up to an H level. As a result, cell data is read from the memory cell C connected to the word line WL, and the potential of the bit line BL becomes slightly higher than the potential of the bit line /BL. When the sense amplifier enable signal LE is set high under this situation, the transistors Tr5 and Tr6 turn on, supplying the high and low potential supply voltages PSG and NSG to the sense amplifier 9. Consequently, the sense amplifier 9 is enabled, increasing the potential difference between the bit lines BL and /BL allowing cell data to be output as output data Dout via the sense amplifier and I/O gate 7 and the I/O buffer circuit 2. Next, when the potential of the selected word line WL and the sense amplifier enable signal LE are pulled low, the sense amplifier 9 becomes disabled, resetting the potentials of the bit lines BL and /BL to the same level.
In self-refresh mode of cell data, each memory cell C is periodically selected by the self-refresh controller 8. Cell data read onto the bit lines BL and /BL from the selected memory cell C is latched by the sense amplifier 9 connected to those bit lines. Based on the latched data in the sense amplifier 9, data is written in the selected memory cell C to accomplish the self-refreshing operation.
In a DRAM with a large memory capacity, numerous sense amplifiers 9 are simultaneously enabled, for example, in the aforementioned read mode. This action results in the generation of two types of power supply related noise: noise N1, which temporarily decreases the voltage level of the power supply Vcc, and noise N2, which temporarily increases the voltage level of the power supply Vss. Both are respectively indicated by the broken lines in FIG. 3. Such power supply noises N1 and N2 tend to induce circuits peripheral to the memory cell 6 to malfunction.
In a typical DRAM, a single self refreshing operation performed on a memory cell requires 1024 cycles of self refreshing over a 128 ms period. That is, each memory cell is self-refreshed at the time interval of 128 ms. If the DRAM has a memory capacity of 1M bits, about 1000 bits of memory cells are simultaneously self-refreshed per cycle, so that about 1000 sense amplifiers are simultaneously enabled. With a memory capacity of 4M bits, about 4000 bits of memory cells are simultaneously self-refreshed per cycle, so that about 4000 sense amplifiers are simultaneously enabled. This illustrates that as the memory capacity of the DRAM increases, so does the number of the sense amplifiers operating simultaneously. The larger capacity DRAMs, therefore, experience notable peak current values between the individual simultaneously operating sense amplifiers and their respective power supplies. This results in unwanted and significant power supply related noises N1 and N2.